Charge-mode parallel architecture for vector-matrix multiplication
نویسندگان
چکیده
منابع مشابه
Charge-Mode Parallel Architecture for Matrix-Vector Multiplication
An internally analog, e x t e d y digital architecture for matrix-vector multiplication is presented. Fully parallel processing allows for high data throughput and minimal latency. The analog architecture incorporates an array of chargemode analog computational cells with dynamic storage and mwparallel fiash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage elemen...
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An internally analog, externally digital architecture for parallel vector–matrix multiplication is presented. A threetransistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combini...
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ژورنال
عنوان ژورنال: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
سال: 2001
ISSN: 1057-7130
DOI: 10.1109/82.974781